Energy Markets for N-SIDE

Camel curve ‘day ahead price’ prediction using Extreme Boost Gradient machine learning, here compared to the realized price.

Magnitude: Energy Price Prediction & Gas/Electricity Heterogenous markets

In the Magnitude H2020 project Magnitude, we defined multi-carrier market products, for example, for energy conversion, mainly from gas to electricity, for imagined future multi-carrier markets. The rationale is that gas and electricity have complementary advantages. For example gas can be stored more cheaply than electricity but its transport is more expensive. We proved that a market able to consider benefits and flexibilities of both carriers at once over a time horizon and given network can lead to better optima and reduced prices compared to separated gas and electricity markets.
To work with realistic bid prices in the markets I also wrote an ML based engine that does price prediction for the 24 hours of the next day and trained this on both gas and electricity historical data for 96 different markets.

Optimised Powerflow for all of Northern Italy

SmartNet: Electricity Market and Power Flow Optimisation

We constructed these simulations for large regions of the TSO network in the 3 pilot countries: Italy, Denmark and Spain. These networks also included DSO distribution networks connected to the TSO network. Within the N-SIDE market clearing block, power flow optimisations were run, with dedicated MIP models for TSO and DSO networks. For each pilot country, 4 seasons and 5 different TSO-DSO coordinations schemes were run. I then ran and monitored about 60 simultaneous simulations running for about 12 to 30 days on as many AWS cloud computers.

SmartNet: Energy Simulation Software Architecture

For the H2020 SmartNet project, I designed the core database scheme and Django backend, as well as architected the framework to cooperate with 7 companies coding in one repository, for a large simulation and optimisation software framework. This framework including blocks like bidding, aggregation, market clearing, disaggregation and a physical layer.

Timetabling and Track Selection for Infrabel

Core Algo, Touch Detection Pattern and Application

TimeTabling: RhinoCeros

While consulting at Infrabel, I also worked and published towards my PhD. I managed to write a system in C++, using MIP solvers, the schedule all Belgian hourly trains in 2 hours calculation time, and reducing the statistically expected passenger time, including statistically expected primary and secondary delays. by 3.8%. I ran the same system on all 100 Danish trains, and after 1 hour calculation time I obtained a reduction of 2.7%.

Platforming: Leopard

I also wrote a system in C++ with a Qt front end, allowing planners to generate an optimal track allocation for any station in Belgium. The system also compares the result graphically with the current plan. It shows that current plans sometimes have 2 trains on two crossing routes toward/from their platform tracks, and that this never happens in my automatically calculated plans.

Consumer Product Software Prototyping for Philips

EnterTaible: Tracking your Hands

Philips Research Eindhoven invented a multi (up to 10 or more hands) touch table consisting of a TV horizontally mounted in a table. It had leds and sensors interleaved around the screen. I wrote up the core C++ computational geometry algorithm software to convert data read from the photodiodes into the set of convex hulls of all the touches. I also participated in R&D to improve the algorithm running time by a factor 4.

SmartFloor: Tracking your Feet

For a large shopping window, Philips Research constructed a 1m by 8m pressure sensitive floor with a measurable pressure byte per square centimeter. I wrote up the software to assemble the data of all connected devices, deduce human feet positions and even recognize people by implementation of a classification algorithm based on 12 features of both feet impressions. Amongst 5 people on which we did supervised training, the correct person could be identified in 98% of the frames. I improved this person identification by multi frame majority voter.

Movie in a Minute Producer

We wrote up a tool that could stitch together fragments of video and audio from different media files and combine it into a movie clip representing a summary of a full length movie. This included video and audio feed in feed out and lip-synching in real time

Container Detection Automation for Camco

Color-bands represent the number of steps needed for convergence of the GPS like sphere intersecting container localisation algorithm.

Container in Cay Crane Localisation Algorithm

I developed for a WIFI network of embedded Camco computers stuck with magnets to a cay-crane, a gps like algorithm that could detect the position of the computer mounted on the spreader picking up the container by measuring the distances of the computers around it. Since this locates the container itself as well, the best positioned computer-connected camera could be derived and asked to picture the container including its ISO number. I implemented an embedded software library to set camera parameters and read images from firewire based cameras with zoom lens.

Freight Train into Containers Separation Algorithm

For Camco, I developed embedded real time software to separate a riding train into containers. This was based on detection of the cylindrically train buffers. I also wrote the embedded software to read out time of flight Sick laser scanners data frames at high speed. Majority voting over ‘container’ or ‘in between container’ frames over multiple frames improved accuracy.

Chip Design

Automation & Prototyping Tools

at Easics

On Chip Processor Grid Message Router & Scheduler

When working at Easics, apart from some ASIC design projects, I wrote up a model to optimally route and schedule messages passing between different ‘Easics Cores’ architected as a ‘compute-communicate‘-systolic system grid.

Worst Case Execution Time Calculator

For the Easics core, I developed a C++ tool that could derive upper bounds for the number of clock cycles that an assembly language program would take during the systolic compute phase. Together with the known cycle accurate scheduling time, a worst case total compute time of the whole processor grid could be accurately predicted.

PCB Design for Processor Grid Emulator

I designed a 12 layer network interface board and a 10 layer matrix board containing large BGA Xilinx FPGAs. Each FPGAs contained an Easics RISC Core and a switch with some routing logic. These boards were interconnectable in a modular way, so that large systems we composable. The system was both software and hardware programmable.